A variety of frequency synthesizers have been developed for use in digital communication systems as reference signal sources or oscillators. However, as newer communication systems are developed for serving larger numbers of users, frequency resolution and noise generation become increasingly significant problems. This is due to the fact that larger numbers of communication channels are desired within given bandwidth allocations which results in continually smaller, minimum, separations between adjacent channels. Therefore, to maintain adequate communication characteristics the reference or mixing frequencies for each channel must be resolved with increasing accuracy and noise and interference must be kept to a minimum.
Direct Digital Synthesizers (DDS) are finding extensive use in advanced digital communication systems especially for generating variable reference frequencies required by frequency hopping and large multi-channel systems or schemes. DDS synthesizers offer relatively high frequency resolution, allow efficient interface with typical digital control circuitry and commands, and provide high speed operation, and low power consumption all of which are a must in satellite and mobile communication systems.
DDS frequency synthesizers typically comprise a digital phase accumulator, a periodic wave function conversion element, in the form of Read Only Memory (ROM) devices, and a Digital-to Analog Converter (DAC). The phase accumulator is used for incrementing a phase angle which is applied at regular intervals to the conversion element which converts accumulated phase angles to a periodic wavefunction amplitude. The wavefunction amplitude, such as the amplitude of a sine function, is then converted into an analog waveform. That is, the instantaneous amplitude at given points during the period of the sine function are computed as digital values from accumulated phase and then transferred to a Digital-to-Analog Converter (DAC) for conversion to an analog signal having the same frequency as the phase angle data.
When digital information, such as a sine amplitude, is converted to analog form, spurious noise is created due to a quantization effect. It is well known that for any digital to analog conversion process that there is an error of .+-.1/2 the smallest quantization step, or Least Significant Bit (LSB) for base two digital data, for DAC input data as it is translated to discrete analog amplitude levels. This error creates spurious and harmonic noise on a periodic basis.
For typical digital conversion, the spurious noise resulting from quantization error generates spectral peaks at several predictable frequencies. These peaks have been found to have an energy level that falls roughly 6 dB per DAC input bit, down in energy level from a desired fundamental output frequency. This reflects a correlation between DAC amplitude resolution and the magnitude of any resulting quantization error. The number of input bits used by the DAC, which determines the DAC resolution, times the -6 dB factor represents the energy level or amplitude of the spurious noise produced during the conversion process. For an 8-bit wide DAC input the peak noise is roughly 48 dB below the fundamental frequency while a 12-bit wide DAC conversion produces roughly a 72 dB difference.
Therefore, to decrease spurious noise peaks in the DAC output and improve frequency resolution for a DDS circuit, the DAC input bit width or resolution can be increased. However, increasing the DAC input resolution means increasing the complexity of the DAC itself which leads to slower speed, increased power consumption, lower reliability and higher costs, none of which are desirable in communication systems. A trade off is reached between the above design factors and the maximum amount of noise a system can withstand for adequate operation.
Several techniques have been employed in an attempt to improve frequency resolution and overcome quantization noise in DDS circuits. Exemplary techniques are found in U.S. Pat. Nos. 4,652,832 and 4,410,954 issued to Steven C. Jasper and Charles Wheatly, III, respectively.
In U.S. Pat. No. 4,410,954, a phase accumulator is employed as a direct digital integrator and the typical sine amplitude look-up table and DAC elements eliminated. A dither signal is added to the input or output of the accumulator to randomly jitter the phase vectors or increments in small steps and spread spectral noise out over the spectrum of interest. This method eliminates quantization and conversion errors associated with the DAC and sine amplitude elements by eliminating those elements. However, this approach also eliminates the ability to achieve higher frequency resolution through the use of advanced sine amplitude conversion techniques.
In U.S. Pat. No. 4,652,832 a digital dither signal is added to the output of a phase accumulator before conversion into sine and cosine data through the use of a series of look-up tables. The accuracy of the conversion process for the sine and cosine amplitude data is said to be improved which leads to lower quantization noise in the subsequent DAC conversion process. However, an increase in accuracy or resolution at intermediate stages does not eliminate the effects of the DAC quantization error.
To adapt to increasing resolution requirements for communication systems and technology, a new method is needed to minimize spurious noise generated in Direct Digital Synthesizers and obtain optimum frequency resolution and system response without increased synthesizer complexity.